Ddr3 Sodimm Memory (Pl) - Xilinx ZC706 User Manual

Table 1-3: I/O Voltage Rails (Cont'd)
XC7Z045 (U1)
Bank
PS Bank 500
PS Bank 501
PS Bank 502
Notes:
1. The ZC706 evaluation board is shipped with V

DDR3 SODIMM Memory (PL)

[Figure 1-2, callout 2]
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM) for
storing user code and data.
• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
• Supply voltage: 1.5V
• Datapath width: 64 bits
• Data rate: Up to 1,600 MT/s
The DDR3 interface is implemented across the PL-side I/O banks. Bank 33 and bank 35 have
a dedicated DCI VRP/N resistor connection. An external 0.75V reference VTTREF_SODIMM is
provided for data interface banks. Any interface connected to these banks that requires the
VTTREF voltage must use this FPGA voltage reference. The connections between the DDR3
memory and the AP SoC are listed in
Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC
XC7Z045 (U1)
Pin
E10
B9
E11
A9
D11
B6
F9
E8
B10
J8
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Net Name Voltage
VCCP1V8 1.8V
ADJ
Table
Net Name I/O Standard
PL_DDR3_A0 SSTL15
PL_DDR3_A1 SSTL15
PL_DDR3_A2 SSTL15
PL_DDR3_A3 SSTL15
PL_DDR3_A4 SSTL15
PL_DDR3_A5 SSTL15
PL_DDR3_A6 SSTL15
PL_DDR3_A7 SSTL15
PL_DDR3_A8 SSTL15
PL_DDR3_A9 SSTL15
www.xilinx.com
Connected To
QSPI0,QSPI1
PHY_IF,SDIO_IF,USB_IF
PS_DDR3_IF
set to 2.5V.
1-4.
DDR3 SODIMM Memory J1
Pin Number
98
97
96
95
92
91
90
86
89
85
Feature Descriptions
Pin Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
18
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