Digital Output; Counter - YASKAWA CPU 013C Manual

Configuration with VIPA SPEED7 Studio
Deployment I/O periphery > Counter
9.6.3.2 Parametrization in SPEED7 Studio
9.6.3.2.1 'I/O addresses'
Sub module Input address
DI16/DO12 136
137
9.6.3.2.2 'Inputs'
'Trigger for process
interrupt'
Input delay

9.6.4 Digital output

9.6.4.1 Overview
9.6.4.2 Parametrization in SPEED7 Studio
9.6.4.2.1 'I/O addresses'
Sub module Output address
DI16/DO12 136
137

9.6.5 Counter

9.6.5.1 Overview
206
Access
BYTE
BYTE
Here you can specify a hardware interrupt for each input for the corresponding edge. The
hardware interrupt is disabled, if nothing is selected (default setting). A diagnostics inter-
rupt is only supported with Hardware interrupt lost.
Here is valid:
n Rising edge: Edge 0-1
n Falling edge: Edge 1-0
The input delay can be configured per channel in groups of 4.
n
n An input delay of 0.1ms is only possible with "fast" inputs, which have a max. input
frequency of 100kHz
for slow inputs is limited to 0.5ms.
n Range of values: 0.1ms / 0.5ms / 3ms / 15ms
n 12xDC 24V, 0.5A
n Sub module 'DI16/DO12'
Ä Chapter 5.5 'Digital output' on page 98
n
Access
BYTE
BYTE
n 4 channels
n Sub module: 'Counter'
Ä Chapter 5.6 'Counting' on page 101
n
Assignment
Digital input I+0.0 ... I+0.7 (X4)
Digital input I+1.0 ... I+1.7 (X4)
Ä 'X4: Connector' on page 40. Within a group, the input delay
Assignment
Digital output Q+0.0 ... Q+0.7 (X5)
Digital output Q+1.0 ... Q+1.3 (X5)
HB300 | CPU | 013-CCF0R00 | en | 16-40
VIPA System SLIO