Parametrization - YASKAWA CPU 013C Manual

Deployment I/O periphery
Pulse width modulation - PWM > Parametrization
Controlling PWM

5.8.5 Parametrization

5.8.5.1 Address assignment
Sub module Input address
Counter 816
820
824
828
Sub module Output address
Counter 816
820
824
828
5.8.5.2 Operating mode per channel
Parameter hardware con-
figuration
142
The pulse width modulation is controlled by the internal gate (I gate). The I gate is iden-
tical to the software gate (SW gate).
SW gate:
open (activate): In the user program by setting SW_EN of SFB 49
close (deactivate): In the user program by resetting SW_EN of SFB 49
If values during the PWM output are changed, the new values will be
issued until the beginning of a new period. A just started period runs
always to the end!
Access
DINT
DINT
DINT
DINT
Access
DWORD
DWORD
DWORD
DWORD
Select via 'Channel' the channel select via 'Operating' the operating mode. The fol-
lowing operating modes are supported:
n Not parameterized: Channel is deactivated
n Ä Chapter 5.6.6.1 'Count continuously' on page 115
n Ä Chapter 5.6.6.2 'Count once' on page 116
Ä Chapter 5.6.6.3 'Count Periodically' on page 119
n
Ä Chapter 5.7 'Frequency measurement' on page 128
n
Ä Chapter 5.8 'Pulse width modulation - PWM' on page 137
n
Depending on the selected operating mode default values are loaded and shown in an
additional register.
Assignment
Channel 0: Counter value / Frequency value
Channel 1: Counter value / Frequency value
Channel 2: Counter value / Frequency value
Channel 3: Counter value / Frequency value
Assignment
reserved
reserved
reserved
reserved
HB300 | CPU | 013-CCF0R00 | en | 16-40
VIPA System SLIO