Port J; 19.10.1 Register Description - Hitachi SH7709S Hardware Manual

19.10

Port J

Port J is an 8-bit input/output port with the pin configuration shown in figure 19.9. Each pin has
an input pull-up MOS, which is controlled by the port J control register (PJCR) in the PFC.
Port J

19.10.1 Register Description

Table 19.17 summarizes the port J register.
Table 19.17 Port J Register
Name
Port J data register
Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either
access this register from the P2 area of logical space or else make an appropriate setting
using the MMU so that this register is not cached.
* When address translation by the MMU does not apply, the address in parentheses
should be used.
PTJ7 (input/output) / STATUS1 (output)
PTJ6 (input/output) / STATUS0 (output)
PTJ5 (input/output)
PTJ4 (input/output)
PTJ3 (input/output) / CASU (output)
PTJ2 (input/output) / CASL (output)
PTJ1 (input/output)
PTJ0 (input/output) / RAS3L (output)
Figure 19.9 Port J
Abbreviation R/W
PJDR R/W
Initial Value Address
H'00 H'04000130
(H'A4000130)*
Access Size
8
607