Hitachi SH7709S Hardware Manual page 723

CKIO
A25 to A16
A12 or A10
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
CKE
DACKn
Figure 23.36 Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 1)
704
Tp Tpw Tr Trw
t
AD
Row address
t t t
AD AD AD
Row
address
t t t
AD AD
Row
address
t
CSD3
t t t
RWD RWD
t t t t
RASD2 RASD2 RASD2 RASD2
t
t t
DQMD
t
t
(High)
t DAKD1
Tc1 Tc2 Tc3 Td4
t
t
Write command
t
AD
Column address
t
t
RWD
t
CASD2
t
DQMD
t
WDD2
BSD
AD
AD
AD
CSD3
RWD
CASD2
DQMD
WDD2
t
BSD
t DAKD1