Clock Operating Modes - Hitachi SH7709S Hardware Manual

9.3

Clock Operating Modes

Table 9.3 shows the relationship between the mode control pin (MD2–MD0) combinations and the
clock operating modes. Table 9.4 shows the usable frequency ranges in the clock operating modes.
Table 9.3 Clock Operating Modes
Pin Values
ModeMD2 MD1 MD0 Source Output
0 0 0 0 EXTAL CKIO
1 0 0 1 EXTAL CKIO
2 0 1 0 Crystal
oscillator
7 1 1 1 CKIO
— Except above Reserved
value
Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by
PLL circuit 2 before being supplied inside the chip. PLL circuit 1 is constantly on. An input clock
frequency of 25 MHz to 66.67 MHz can be used, and the CKIO frequency range is 25 MHz to
66.67 MHz.
Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by
PLL circuit 2 before being supplied inside the chip, allowing a low-frequency external clock to be
used. An input clock frequency of 6.25 MHz to 16.67 MHz can be used, and the CKIO frequency
range is 25 MHz to 66.67 MHz.
Mode 2: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied by
4 by PLL circuit 2 before being supplied inside the chip, allowing a low crystal frequency to be
used. A crystal oscillation frequency of 6.25 MHz to 16.67 MHz can be used, and the CKIO
frequency range is 25 MHz to 66.67 MHz.
Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and
undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL
circuit 1 before being supplied to the chip. In modes 0 to 2, the system clock is generated from the
Clock I/O
PLL2
On/Off On/Off Input
On,
multi-
plication
ratio: 1
On,
multi-
plication
ratio: 4
CKIO On,
multi-
plication
ratio: 4
— Off
PLL1 Divider 1 Divider 2 CKIO
Input
On PLL1 PLL1
output
On PLL1 PLL1
output
On PLL1 PLL1
output
On PLL1 PLL1
output
Frequency
(EXTAL)
(EXTAL) × 4
(Crystal) × 4
(CKIO)
211