Peripheral Module Signal Timing - Hitachi SH7709S Hardware Manual

23.3.8

Peripheral Module Signal Timing

Table 23.8 Peripheral Module Signal Timing
(VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C)
Module Item
TMU, Timer input setup time
RTC Timer clock input setup time
Timer clock
pulse width
Oscillation settling time
SCI Input clock
cycle
Input clock rise time
Input clock fall time
Input clock pulse width
Transmission data delay time
Receive data setup time
(clock synchronization)
Receive data hold time
(clock synchronization)
RTS delay time
CTS setup time
(clock synchronization)
CTS hold time
(clock synchronization)
Port Output data delay time
Input data setup time
Input data hold time
Input data setup time
Input data hold time
Input data setup time
Input data hold time
DREQ setup time
DMAC
DREQ hold time
DRAK delay time
Note: *1 Pcyc is the P clock cycle.
Edge specification
Both edge specification
Asynchronization
Clock synchronization
to 66
Symbol Min Max
t 15 —
TCLKS
t 15 —
TCKS
t 1.5 —
TCKWH
t 2.5 —
TCKWL
t 3 —
ROSC
t 4 —
SCYC
6 —
t — 1.5
SCKR
t — 1.5
SCKF
t 0.4 0.6
SCKW
t — 100
TXD
t 100 —
RXS
t 100 —
RXH
t — 100
RTSD
t 100 —
CTSS
t 100 —
CTSH
t — 17
PORTD
t 15 —
PORTS1
t 8 —
PORTH1
t tcyc + —
PORTS2
15
t 8 —
PORTH2
t 3×tcyc —
PORTS3
+ 15
t 8 —
PORTH3
t 6 —
DRQS
t 4 —
DREQH
t — 10
DRAKD
Unit Figure
ns 23.47
23.48
Pcyc
s 23.49
1
Pcyc* 23.50
23.51
23.50
tscyc
ns 23.51
ns 23.52
ns 23.53
23.54
715