Hitachi SH7709S Hardware Manual page 188

Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
Bit 6: PCBB Description
0 PC break of channel B is set before instruction execution
1 PC break of channel B is set after instruction execution
Bits 5 and 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Sequence Condition Select (SEQ): Selects two conditions of channels A and B as
independent or sequential.
Bit 3: SEQ Description
0 Channels A and B are compared under the independent condition (Initial value)
1 Channels A and B are compared under the sequential condition (channel A, then
channel B)
Bit 2 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—The Number of Execution Times Break Enable (ETBE): Enable the execution-times
break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the
number of break conditions matches with the number of execution times that is specified by the
BETR register.
Bit 0: ETBE Description
0 The execution-times break condition is masked on channel B
1 The execution-times break condition is enabled on channel B
(Initial value)
(Initial value)
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