Hitachi SH7709S Hardware Manual page 17

19.12.1 Register Description.............................................................................................. 611
19.12.2 Port L Data Register (PLDR)................................................................................ 612
19.13 SC Port................................................................................................................................ 613
19.13.1 Register Description.............................................................................................. 613
19.13.2 Port SC Data Register (SCPDR) ........................................................................... 614
Section 20 A/D Converter
20.1 Overview ............................................................................................................................ 617
20.1.1 Features ................................................................................................................. 617
20.1.2 Block Diagram ...................................................................................................... 618
20.1.3 Input Pins .............................................................................................................. 619
20.1.4 Register Configuration .......................................................................................... 620
20.2 Register Descriptions.......................................................................................................... 621
20.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 621
20.2.2 A/D Control/Status Register (ADCSR) ................................................................ 622
20.2.3 A/D Control Register (ADCR).............................................................................. 624
20.3 Bus Master Interface .......................................................................................................... 626
20.4 Operation ............................................................................................................................ 627
20.4.1 Single Mode (MULTI = 0).................................................................................... 627
20.4.2 Multi Mode (MULTI = 1, SCN = 0) ..................................................................... 629
20.4.3 Scan Mode (MULTI = 1, SCN = 1) ...................................................................... 631
20.4.4 Input Sampling and A/D Conversion Time .......................................................... 633
20.4.5 External Trigger Input Timing .............................................................................. 634
20.5 Interrupts ............................................................................................................................ 635
20.6 Definitions of A/D Conversion Accuracy .......................................................................... 635
20.7 Usage Notes........................................................................................................................ 636
20.7.1 Setting Analog Input Voltage................................................................................ 636
20.7.2 Processing of Analog Input Pins ........................................................................... 636
20.7.3 Access Size and Read Data ................................................................................... 637
Section 21 D/A Converter
21.1 Overview ............................................................................................................................ 639
21.1.1 Features ................................................................................................................. 639
21.1.2 Block Diagram ...................................................................................................... 639
21.1.3 I/O Pins.................................................................................................................. 640
21.1.4 Register Configuration .......................................................................................... 640
21.2 Register Descriptions.......................................................................................................... 641
21.2.1 D/A Data Registers 0 and 1 (DADR0/1) .............................................................. 641
21.2.2 D/A Control Register (DACR).............................................................................. 641
21.3 Operation ............................................................................................................................ 643
Section 22 Hitachi User Debugging Interface (H-UDI)
22.1 Overview ............................................................................................................................ 645
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