Hitachi SH7709S Hardware Manual page 720

Tp
CKIO
t
AD
A25 to A16
t
AD
A12 or A10
A15 to A0
t
CSD3
CSn
t
RWD
RD/WR
t
RASD2
RAS
CAS
t
DQMD
DQMxx
D31 to D0
BS
CKE
(High)
t DAKD1
DACKn
Figure 23.33 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1)
Tpw Tr Tc1 Tc2/Td1
Row address
t t
AD AD
Row
Read command
address
t t
AD AD
Row
Column address
address
t
RWD
t t t
RASD2 RASD2 RASD2
t
CASD2
t
DQMD
t
RDS2
t
BSD
Tc3/Td2 Tc4/Td3 Td4
t
AD
t
AD
t
AD
t
CSD3
t
RWD
t
CASD2
t
DQMD
t t t
RDH2 RDS2 RDH2
t
BSD
t DAKD1
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