Hitachi SH7709S Hardware Manual page 715

CKIO
A25 to A16
A12 or A10
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
CKE
DACKn
Figure 23.28 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write × 4),
696
Tr Tc1 Tc2
tAD
Row address
tAD tAD
Row
Write command
address
tAD tAD
Row
Column address (1-4)
address
tCSD3
tRWD tRWD
tRASD2 tRASD2
tCASD2
tDQMD
tWDD2
tWDD2
tBSD
(High)
t DAKD1
RCD = 0, TPC = 1, TRWL = 0)
Tc3 Tc4 (Trwl) (Tpc)
tAD
tAD tAD
Write A
command
tAD
tCSD3
tRWD
tCASD2
tDQMD
tWDH2
tBSD
t DAKD1
(Tpc)