Hitachi SH7709S Hardware Manual page 710

CKIO
A25 to A16
A12 or A10
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
CKE
DACKn
Figure 23.23 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1)
Tr Trw Trw
tAD
Row address
tAD tAD
Row address
tAD tAD
Row address
tCSD3
tRWD
tRASD2 tRASD2
tCASD2
tDQMD
(High)
t DAKD1
Tc1 Tcw Td1 (Tpc)
tAD
tAD
Read A
command
tAD
Column address
tCSD3
tRWD
tCASD2
tDQMD
tRDS2 tRDH2
tBSD tBSD
t DAKD1
(Tpc)
691