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Table 2.5 lists the SH7709S instruction code formats.
Table 2.5
Instruction Code Format
Item
Format
Instruction
OP.Sz SRC,DEST
mnemonic
MSB ↔ LSB
Instruction
code
→, ←
Operation
summary
(xx)
M/Q/T
&
|
^
~
<<n, >>n
Privileged
mode
Execution
cycles
T bit
Note: * Scaling (×1, ×2, ×4) is performed according to the instruction operand size.
38
Explanation
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
...........
1111: R15
iiii: Immediate data
dddd: Displacement*
Direction of transfer
Memory operand
Flag bits in SR
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit shift
Indicates whether privileged mode applies
Value when no wait states are inserted
The execution cycles listed in the table are minimums. The
actual number of cycles may be increased in cases such
as the followsing:
1. When contention occurs between instruction fetches
and data access
2. When the destination register of the load instruction
(memory → register) and the register used by the next
instruction are the same
Value of T bit after instruction is executed
—: No change
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