Hitachi SH7709S Hardware Manual page 721

Figure 23.34 Synchronous DRAM Burst Write Bus Cycle
702
Tc1 Tc2
CKIO
t
AD
Row address
A25 to A16
t
AD
Write command
A12 or A10
t
AD
Column address
A15 to A0
t
CSD3
CSn
t
RWD
RD/WR
t
RASD2
RAS
t
CASD2
CAS
t
DQMD
DQMxx
t
WDD2
D31 to D0
t
BSD
BS
CKE
(High)
t DAKD1
DACKn
(RAS Down, Same Row Address)
Tc3 Tc4
t
AD
t
AD
t
AD
t
CSD3
t
RWD
t
RASD2
t
CASD2
t
DQMD
t
WDD2
t
BSD
t DAKD1