Register Descriptions; A/D Data Registers A To D (Addra To Addrd) - Hitachi SH7709S Hardware Manual

20.2

Register Descriptions

20.2.1

A/D Data Registers A to D (ADDRA to ADDRD)

Upper register: H
Bit:
AD9
Initial value:
R/W:
Lower register: L
Bit:
AD1
Initial value:
R/W:
n = A to D
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte (bits 7 to 0) of the A/D data register. The lower 2 bits are stored in the lower byte (bits 7 and
6). Bits 5 to 0 of an A/D data register are reserved bits that are always read as 0. Table 20.3
indicates the pairings of analog input channels and A/D data registers.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 20.3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0
AN0
AN1
AN2
AN3
7 6 5
AD8 AD7
0 0 0
R R R
7 6 5
AD0 —
0 0 0
R R R
Group 1
AN4
AN5
AN6
AN7
4 3 2
AD6 AD5 AD4
0 0 0
R R R
4 3 2
— — —
0 0 0
R R R
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
1 0
AD3 AD2
0 0
R R
1 0
— —
0 0
R R
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