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16.2
Register Descriptions
16.2.1
Receive Shift Register (SCRSR)
The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into
SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one
byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register.
The CPU cannot read or write to SCRSR directly.
Bit:
R/W:
16.2.2
Receive FIFO Data Register (SCFRDR)
The 16-byte receive FIFO data register (SCFRDR) stores serial receive data. The SCIF completes
the reception of one byte of serial data by moving the received data from the receive shift register
(SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored.
The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the
SCFRDR, the value is undefined. When this register is full of receive data, subsequent serial data
is lost.
Bit:
R/W:
16.2.3
Transmit Shift Register (SCTSR)
The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the
transmit FIFO data register (SCFTDR) into SCTSR, then transmits the data serially from the TxD
pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next
transmit data from SCFTDR into SCTSR and starts transmitting again. The CPU cannot read or
write to SCTSR directly.
Bit:
R/W:
7
6
5
—
—
—
7
6
5
R
R
R
7
6
5
—
—
—
4
3
2
—
—
—
4
3
2
R
R
R
4
3
2
—
—
—
1
0
—
—
1
0
R
R
1
0
—
—
521
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