Acceptance Of Exceptions - Hitachi SH7709S Hardware Manual

Table 4.2 Exception Event Vectors (cont)
Exception Current
Type Instruction Exception Event
General Completed
exception
events
General Completed
interrupt
requests
Notes: *1 Priorities are indicated from high to low, 1 being the highest and 4 the lowest.
*2 The user defines the break point traps. 1 is a break point before instruction execution
and 11 is a break point after instruction execution. For an operand break point, use 11.
*3 Use software to specify relative priorities of external hardware interrupts and peripheral
module interrupts (see section 6, Interrupt Controller (INTC)).
4.2.3

Acceptance of Exceptions

Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All
exception events are prioritized to establish an acceptance order whenever two or more exception
events occur simultaneously. The power-on reset and manual reset do not occur simultaneously, so
they have the same priority.
All general exception events occur in a relative order in the execution sequence of an instruction
(i.e. execution order), but are handled at priority level 2 in instruction-stream order (i.e. program
order), where an exception detected in a preceding instruction is accepted prior to an exception
detected in a subsequent instruction.
Three general exception events (reserved instruction code exception, unconditional trap, and
illegal slot instruction exception) are detected in the decode stage (ID stage) of different
instructions and are mutually exclusive events in the instruction pipeline. They have the same
execution priority. Figure 4.2 shows the order of general exception acceptance.
92
Priority*
User breakpoint trap 2
DMA address error 2
Nonmaskable 3
interrupt
External hardware 4*
interrupt
H-UDI interrupt 4*
Exception Vector
1
Order Address
2
n* —
12 —
— —
3
— —
3
— —
Vector
Offset
H'00000100
H'00000100
H'00000600
H'00000600
H'00000600