Hitachi SH7709S Hardware Manual page 311

CKIO
A25 to A0
CSn
RD/WR
RD
Read
D31 to D0
WEn
Write
D31 to D0
WAIT
BS
Figure 10.19 Basic Timing for Synchronous DRAM Burst Write
Single Write: The basic timing chart for write access is shown in figure 10.20. In a single write
operation, following the Tr cycle in which ACTV command output is performed, a WRITA
command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write
data is output at the same time as the write command. In case of the write with auto-precharge
command, precharging of the relevant bank is performed in the synchronous DRAM after
completion of the write command, and therefore no command can be issued for the same bank
until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in
a read access, cycle Trwl is also added as a wait interval until precharging is started following the
write command. Issuance of a new command for the same bank is deferred during this interval.
The number of Trwl cycles can be specified by the TRWL bits in MCR.
292
T1 Tw
Wait state by WAIT
signal input
Tw Tw T2