Hitachi SH7709S Hardware Manual page 329

Superh risc engine
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T1
TW
TW
TB2
TB1
TW
TB2
TB1
T2
CKIO
A25 to A4
A3 to A0
CSn
RD/WR
RD
D31 to
D0
BS
WAIT
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 10.31 Burst ROM Wait Access Timing
310

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