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Table 2.3
Instruction Formats (cont)
Instruction Format
nmd
15
format
xxxx
nnnn
d format
15
xxxx
xxxx
d12 format
15
xxxx
dddd
nd8 format
15
xxxx
nnnn
15
i format
xxxx
xxxx
ni format
15
xxxx
nnnn
Note: In a multiply-and-accumulate instruction, nnnn is the source register.
34
Source
Operand
mmmm: register
0
direct
dddd
mmmm
mmmmdddd:
register indirect
with displacement
0
dddddddd: GBR
indirect with
dddd
dddd
displacement
R0 (register
direct)
dddddddd:
PC-relative with
displacement
dddddddd:
PC-relative
0
dddddddddddd:
PC-relative
dddd
dddd
0
dddddddd:
PC-relative with
dddd
dddd
displacement
0
iiiiiiii: immediate
i i i i
i i i i
iiiiiiii: immediate
iiiiiiii: immediate
0
iiiiiiii: immediate
i i i i
i i i i
Destination
Instruction
Operand
Example
nnnndddd:
MOV.L
register
Rm,@(disp,Rn)
indirect with
displacement
nnnn: register
MOV.L
direct
@(disp,Rm),Rn
R0 (register
MOV.L
direct)
@(disp,GBR),R0
dddddddd:
MOV.L
GBR indirect
R0,@(disp,GBR)
with
displacement
R0 (register
MOVA
direct)
@(disp,PC),R0
—
BF
—
BRA
(label = disp +
PC)
nnnn: register
MOV.L
direct
@(disp,PC),Rn
Indexed GBR
AND.B
indirect
#imm,
@(R0,GBR)
R0 (register
AND
direct)
#imm,R0
—
TRAPA #imm
nnnn: register
ADD
direct
#imm,Rn
label
label
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