I/O Pins; Register Configuration - Hitachi SH7709S Hardware Manual

21.1.3

I/O Pins

Table 21.1 summarizes the D/A converter's input and output pins.
Table 21.1 D/A Converter Pins
Pin Name
Analog power supply pin
Analog ground pin
Analog output pin 0
Analog output pin 1
21.1.4

Register Configuration

Table 21.2 summarizes the D/A converter's registers.
Table 21.2 D/A Converter Registers
Name
D/A data register 0
D/A data register 1
D/A control register
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
*1 Lower 16 bits of the address
*2 When address translation by the MMU does not apply, the address in parentheses
should be used.
640
Abbreviation I/O
AVcc Input
AVss Input
DA0 Output
DA1 Output
Abbreviation
DADR0
DADR1
DACR
Function
Analog power supply
Analog ground and reference voltage
Analog output, channel 0
Analog output, channel 1
R/W Initial Value
R/W H'00
R/W H'00
R/W H'1F
1
Address*
H'040000A0
2
(H'A40000A0)*
H'040000A2
2
(H'A40000A2)*
H'040000A4
2
(H'A40000A4)*