Hitachi SH7709S Hardware Manual page 714

CKIO
tAD
A25 to A16
tAD
A12 or A10
tAD
A15 to A0
tCSD1
CSn
tRWD
RD/WR
tRASD2
RAS
CAS
DQMxx
D31 to D0
BS
CKE
t DAKD1
DACKn
Figure 23.27 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1)
Tr Trw Trw Tc1
Row address
tAD tAD
Row Write A
address command
tAD tAD
Row Column
address address
tRWD
tRASD2
tCASD2
tDQMD
tWDD2
tBSD
(High)
(Trwl) (Trwl) (Tpc)
tAD
tAD
tAD
tCSD1
tRWD
tCASD2
tDQMD
tWDH2
tBSD
t DAKD1
(Tpc)
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