Hitachi SH7709S Hardware Manual page 478

Superh risc engine
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Table 14.9 Serial Mode Register Settings and SCI Communication Formats
SCSMR Settings
Bit 7
Bit 6
Bit 5
Bit 2
C/A
CHR
PE
MP
0
0
0
0
1
1
0
1
0
*
1
*
1
*
*
1
*
*
*
Note: Asterisks (*) indicate don't-care bits.
Table 14.10 SCSMR and SCSCR Settings and SCI Clock Source Selection
SCSMR
SCSCR Settings
Bit 7
Bit 1
Bit 0
C/A
CKE1
CKE0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Bit 3
STOP
Mode
0
Asynchronous
1
0
1
0
1
0
1
0
Asynchronous
(multiprocessor
1
format)
0
1
*
Synchronous
Clock
Mode
Source
Asynchronous
Internal
mode
External
Synchronous
Internal
mode
External
SCI Communication Format
Data
Parity
Multipro-
Length
Bit
cessor Bit
8-bit
Not set
Not set
Set
7-bit
Not set
Set
8-bit
Not set
Set
7-bit
8-bit
Not set
SCI Transmit/Receive Clock
SCK
Pin Function
SCI does not use the SCK pin
Outputs a clock with frequency
matching the bit rate
Inputs a clock with frequency 16
times the bit rate
Outputs the synchronous clock
Inputs the synchronous clock
Stop Bit
Length
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
None
459

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