Hitachi SH7709S Hardware Manual page 371

Superh risc engine
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(DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon input of a transfer
request signal. The source of the transfer request does not have to be the data transfer source or
destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's
receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source
must be the SCI's transmit data register (TDR). If the transfer requester is the A/D converter, the
data transfer source must be the A/D data register (ADDR).
Table 11.4 Selecting On-Chip Peripheral Module Request Modes with RS3-0 Bits
RS3 RS2 RS1 RS0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
ADDR: A/D data register of A/D converter
Note: * External memory, memory-mapped external device, on-chip peripheral module (This
applies only to IrDA, SCIF, A/D converter, D/A converter, and I/O ports.)
When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt
enable bits must be set to output the interrupt signals.
If the interrupt request signal of the on-chip peripheral module is used as a DMA transfer request
signal, an interrupt is not sent to the CPU.
The DMA transfer request signals in table 11.4 are automatically discontinued when the
corresponding DMA transfer is performed. If cycle-steal mode is being employed, they are
withdrawn at the first transfer; if burst mode is being used, they are discontinued at the last
transfer.
352
DMA
Transfer
Request
Source
DMA Transfer Request Signal Source
IrDA
TXI1 (IrDA transmit-data-empty
transmitter
interrupt transfer request)
IrDA
RXI1 (IrDA receive-data-full
receiver
interrupt transfer request)
SCIF
TXI2 (SCIF transmit-data-empty
transmitter
interrupt transfer request)
SCIF
RXI2 (SCIF receive-data-full
receiver
interrupt transfer request)
A/D
ADI (A/D conversion end
converter
interrupt)
CMT
CMI (Compare match timer
interrupt)
Desti-
nation Bus Mode
Any*
TDR1
Cycle-steal
RDR1
Any*
Cycle-steal
Any*
TDR2
Cycle-steal
RDR1
Any*
Cycle-steal
ADDR
Any*
Cycle-steal
Any*
Any*
Burst/
cycle-steal

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