Block Diagram - Hitachi SH7709S Hardware Manual

6.1.2

Block Diagram

Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRL3–IRL0
IRLS3–IRLS0
IRQ0–IRQ5
PINT0–PINT15
DMAC
IrDA
SCIF
SCI
ADC
TMU
RTC
WDT
REF
H-UDI
Legend
TMU : Timer unit
RTC : Realtime clock unit
SCI : Serial communication interface
IrDA : Serial communication interface (with IrDA)
SCIF : Serial communication interface (with FIFO)
WDT : Watchdog timer
REF : Refresh requests in the bus state controller
ICR : Interrupt control register
IPRA–IPRE : Interrupt priority registers A–E
SR : Status register
DMAC : Direct memory access controller
ADC : Analog-to-digital converter
H-UDI : Hitachi user-debugging interface
122
4
Input/output
control
4
6
16
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request/
refresh request)
(Interrupt request)
ICR
Figure 6.1 Block Diagram of INTC
Com-
parator
Priority
identifier
IPR
IPRA–IPRE
Bus
interface
INTC
Interrupt
request
SR
3 2 1 0
CPU