Overview Of Wdt; Block Diagram Of Wdt; Register Configuration - Hitachi SH7709S Hardware Manual

9.6

Overview of WDT

9.6.1

Block Diagram of WDT

Figure 9.2 shows a block diagram of the WDT.
Standby
cancellation
Internal
reset
request
Interrupt
request
Legend
WTCSR: Watchdog timer control/status register
WTCNT: Watchdog timer counter
9.6.2

Register Configuration

The WDT has two registers that select the clock, switch the timer mode, and perform other
functions. Table 9.5 shows the WDT registers.
Table 9.5 Register Configuration
Name
Watchdog timer counter
Watchdog timer
control/status register
Note: * Write with word access. Write with H'5A and H'A5, respectively, in the upper byte. Byte or
longword writes are not possible. Read with byte access.
218
WDT
Standby
control
Reset
control
Clock selection
Overflow
Interrupt
control
WTCSR
Bus interface
Figure 9.2 Block Diagram of WDT
Abbreviation R/W
WTCNT R/W* H'00
WTCSR R/W* H'00
Divider
Clock selector
Clock
WTCNT
Initial Value Address
H'FFFFFF84
H'FFFFFF86
Standby
mode
Peripheral
clock
Access Size
R: 8;
W: 16*
R: 8;
W: 16*