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3. IRQ Pin Interrupts
Conditions: The IRQ pin is asserted, SR.IMASK is lower than the IRQ priority level, and the
BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to
SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to the
interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to VBR + H'0600. The received level is not set in the interrupt mask bits
in SR. See section 6, Interrupt Controller (INTC), for more information.
4. PINT Pin Interrupts
Conditions: The PINT pin is asserted, the interrupt mask bits in SR. is lower than the PINT
priority level, and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to
SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to the
interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits of SR are set to 1
and a branch occurs to VBR + H'0600. The received level is not set in the interrupt mask bits
in SR. See section 6, Interrupt Controller (INTC), for more information.
5. On-Chip Peripheral Interrupts
Conditions: The interrupt mask bits in SR are lower than the on-chip module (TMU, RTC,
SCI0, SCI1, SCI2, A/D, DMAC, CPG, REF) interrupt level and the BL bit in SR is 0. The
interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to
SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to the
interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC), for more
information.
6. H-UDI Interrupt
Conditions: An H-UDI interrupt command is input (see section 22.4.4, H-UDI Interrupt),
SR.IMASK is lower than 15, and the BL bit in SR is 0. The interrupt is accepted at an
instruction boundary.
Operations: The PC value after the instruction that accepts the interrupt is saved to SPC. SR at
the point the interrupt is accepted is saved to SSR. H'5E0 is set to INTEVT and INTEVT2. The
BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. See section 6,
Interrupt Controller (INTC), for more information.
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