Hitachi SH7709S Hardware Manual page 274

Bits 9, 3, and 2—Area 5 OE/WE Negate Address Delay (A5TEH2, A5TEH1, A5TEH0):
Specify the address hold delay time from OE/WE negation for the PCMCIA interface connected
to area 5.
Bit 9: Bit 3:
A5TEH2 A5TEH1
0 0
1
1 0
1
Bits 8, 1, and 0—Area 6 OE/WE Negate Address Delay (A6TEH2, A6TEH1, A6TEH0):
Specify the address hold delay time from OE/WE negation for the PCMCIA interface connected
to area 6.
Bit 8: Bit 1:
A6TEH2 A6TEH1
0 0
1
1 0
1
Bit 2:
A5TEH0 Description
0 0.5-cycle delay
1 1.5-cycle delay
0 2.5-cycle delay
1 3.5-cycle delay
0 4.5-cycle delay
1 5.5-cycle delay
0 6.5-cycle delay
1 7.5-cycle delay
Bit 0:
A6TEH0 Description
0 0.5-cycle delay
1 1.5-cycle delay
0 2.5-cycle delay
1 3.5-cycle delay
0 4.5-cycle delay
1 5.5-cycle delay
0 6.5-cycle delay
1 7.5-cycle delay
(Initial value)
(Initial value)
255