Table A.6
Pin States (Burst ROM/Big Endian)
Pin
CS6 to CS2, CS0
RD
R
W
RD/WR
R
W
BS
RAS3U/PTE[2]
RAS3L/PTJ[0]
CASL/PTJ[2]
CASU/PTJ[3]
WE0/DQMLL
R
W
WE1/DQMLU/WE
R
W
WE2/DQMUL/ICIORD/
R
PTK[6]
W
WE3/D QM U U /ICIOWR/ R
PTK[7]
W
CE2A/PTE[4]
CE2B/PTE[5]
CKE/PTK[5]
WAIT
IOIS16/PTG[7]
A25 to A0
D7 to D0
D15 to D8
D31 to D16
8-Bit Bus Width
Byte/Word/Long-
Byte Access
word Access
(Address 2n)
Enabled
Enabled
Low
Low
—
—
High
High
—
—
Enabled
Enabled
High
High
High
High
High
High
High
High
High
High
—
—
High
High
—
—
High
High
—
—
High
High
—
—
High
High
High
High
Disabled
Disabled
*1
Enabled
Enabled
Disabled
Disabled
Address
Address
Valid data
Invalid data
*2
High-Z
Valid data
*2
High-Z
High-Z
16-Bit Bus Width
Byte Access
(Address 2n + 1)
Enabled
Low
—
High
—
Enabled
High
High
High
High
High
—
High
—
High
—
High
—
High
High
Disabled
*1
*1
Enabled
Disabled
Address
Valid data
Invalid data
*2
*2
High-Z
Word/Longword
Access
Enabled
Low
—
High
—
Enabled
High
High
High
High
High
—
High
—
High
—
High
—
High
High
Disabled
*1
Enabled
Disabled
Address
Valid data
Valid data
*2
High-Z
739