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Table A.1
Pin States during Resets, Power-Down States, and Bus-Released State (cont)
Category
Pin
ASEMD0/PTG[6]
Port
PTJ[1]
PTE[1]*
PTE[6]
PTE[3]
PTJ[4]
PTJ[5]
Analog
AN[5:0]/PTL[5:0]
AN[6:7]/DA[1:0]/
PTL[6:7]
I:
Input
O: Output
H: High-level output
L: Low-level output
Z: High impedance
P: Input or output depending on register setting
K: Input pin is high impedance, output pin holds its state
V: I/O buffer off, pull-up MOS on
Notes: *1 Depending on the clock mode (MD2–MD0 setting).
*2 Z when the port function is used.
*3 K or P when the port function is used.
*4 K or P when the port function is used. Z or O when the port function is not used
depending on register setting.
*5 K or P when the port function is used. I or O when the port function is not used
depending on register setting.
*6 Depending on register setting.
*7 I or O when the port function is used.
*8 Input Schmitt buffers and pull-up MOS of IRQ[5:0] and ADTRG are on; other inputs are
off.
*9 O when DA output is enabled; otherwise I depending on register setting.
*10 In standby mode, Z or L depending on register setting.
*11 In standby mode, Z or H depending on register setting.
*12 O when DA output is enabled; Z otherwise.
*13 In a power-on reset, leave open or input a high level.
726
Power-On
Reset
I
H
13
V
V
V
H
H
Z
Z
Reset
Power-Down
Manual
Reset
Standby
I
Z
3
4
OP*
ZOK*
3
4
OP*
ZOK*
3
4
OP*
ZOK*
3
4
OP*
ZOK*
3
4
OP*
ZOK*
3
4
OP*
ZOK*
7
ZI*
Z
7
12
ZI*
OZ*
Bus
Sleep
Released
I
I
3
4
OP*
ZOP*
3
4
OP*
ZOP*
3
4
OP*
ZOP*
3
4
OP*
ZOP*
3
4
OP*
ZOP*
3
4
OP*
ZOP*
I
I
9
9
IO*
IO*
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