Hitachi SH7709S Hardware Manual page 9

Section 7 User Break Controller
7.1 Overview ............................................................................................................................ 153
7.1.1 Features ................................................................................................................. 153
7.1.2 Block Diagram ...................................................................................................... 154
7.1.3 Register Configuration .......................................................................................... 155
7.2 Register Descriptions.......................................................................................................... 156
7.2.1 Break Address Register A (BARA) ...................................................................... 156
7.2.2 Break Address Mask Register A (BAMRA)......................................................... 157
7.2.3 Break Bus Cycle Register A (BBRA) ................................................................... 158
7.2.4 Break Address Register B (BARB) ...................................................................... 160
7.2.5 Break Address Mask Register B (BAMRB) ......................................................... 161
7.2.6 Break Data Register B (BDRB) ............................................................................ 162
7.2.7 Break Data Mask Register B (BDMRB)............................................................... 163
7.2.8 Break Bus Cycle Register B (BBRB) ................................................................... 164
7.2.9 Break Control Register (BRCR) ........................................................................... 166
7.2.10 Execution Times Break Register (BETR) ............................................................. 170
7.2.11 Branch Source Register (BRSR) ........................................................................... 171
7.2.12 Branch Destination Register (BRDR) ................................................................... 172
7.2.13 Break ASID Register A (BASRA)........................................................................ 173
7.2.14 Break ASID Register B (BASRB) ........................................................................ 173
7.3 Operation Description ........................................................................................................ 174
7.3.1 Flow of the User Break Operation ........................................................................ 174
7.3.2 Break on Instruction Fetch Cycle.......................................................................... 175
7.3.3 Break by Data Access Cycle ................................................................................. 175
7.3.4 Sequential Break ................................................................................................... 176
7.3.5 Value of Saved Program Counter.......................................................................... 176
7.3.6 PC Trace................................................................................................................ 177
7.3.7 Usage Examples .................................................................................................... 178
7.3.8 Notes...................................................................................................................... 182
Section 8 Power-Down Modes
8.1 Overview ............................................................................................................................ 185
8.1.1 Power-Down Modes.............................................................................................. 185
8.1.2 Pin Configuration .................................................................................................. 187
8.1.3 Register Configuration .......................................................................................... 187
8.2 Register Descriptions.......................................................................................................... 187
8.2.1 Standby Control Register (STBCR)...................................................................... 187
8.2.2 Standby Control Register 2 (STBCR2)................................................................. 189
8.3 Sleep Mode......................................................................................................................... 191
8.3.1 Transition to Sleep Mode ...................................................................................... 191
8.3.2 Canceling Sleep Mode .......................................................................................... 191
8.4 Standby Mode .................................................................................................................... 192
8.4.1 Transition to Standby Mode.................................................................................. 192
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