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4.4.3
General Exceptions
When the SH7709S encounters any exception condition other than a reset or interrupt request, it
executes the following operations:
1. The contents of PC and SR are saved to SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt
when the BLMSK bit is 1).
3. The MD bit in SR is set to 1 to place the SH7709S in privileged mode.
4. The RB bit in SR is set to 1.
5. Instruction execution jumps to the vector location designated by either the sum of the vector
base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the
vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke
the exception handler.
4.5
Individual Exception Operations
This section describes the conditions for specific exception handling, and the processor operations.
4.5.1
Resets
• Power-On Reset
Conditions: RESETP low
Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to 1111. The CPU and on-chip peripheral
modules are initialized. See the register descriptions in the relevant sections for details. A
power-on reset must always be performed when powering on. A low level is output from
the RESETOUT pin, and a high level is output from the STATUS0 and STATUS1 pins.
• Manual Reset
Conditions: RESETM low
Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set
to 1 and the interrupt mask bits (I3 to I0) are set to 1111. The CPU and on-chip peripheral
modules are initialized. See the register descriptions in the relevant sections for details. A
low level is output from the RESETOUT pin, and a high level is output from the
STATUS0 and STATUS1 pins.
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