Lcd Power Sequencing; Table 6-14: Passive/Tft Power-On Sequence Timing; Figure 6-11: Passive/Tft Power-On Sequence Timing - Epson S1D13706 Technical Manual

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6.3 LCD Power Sequencing

6.3.1 Passive/TFT Power-On Sequence
GPO*
Power Save
Mode Enable**
(REG[A0h] bit 0)
LCD Signals***
*It is recommended to use the general purpose output pin GPO to control the LCD bias power.
**The LCD power-on sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 0.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Symbol
t1
LCD signals active to LCD bias active
t2
Power Save Mode disabled to LCD signals active
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
S1D13706
X31B-A-001-08

Figure 6-11: Passive/TFT Power-On Sequence Timing

Table 6-14: Passive/TFT Power-On Sequence Timing

Parameter
Note
For HR-TFT Power-On/Off sequence information, see Connecting to the Sharp
HR-TFT Panels, document number X31B-G-011-xx.
For D-TFD Power-On/Off sequence information, see Connecting to the Epson D-TFD
Panels, document number X31B-G-012-xx.
t1
t2
Epson Research and Development
Vancouver Design Center
Min Max
Note 1 Note 1
0 20
Hardware Functional Specification
Issue Date: 01/11/13
Units
ns