Sr-D - ABB ACSM1 Firmware Manual

SR-D

(10039)
Illustration
Execution time
Operation
Inputs
Outputs
1.04 µs
When clock input (C) is set to 1, the data input (D) value is stored to the output (O).
When reset input (R) is set to 1, the output is set to 0.
If only set (S) and reset (R) inputs are used, SR-D block acts as an
The output is 1 if the set input (S) is 1. The output will retain the previous output state if
the set input (S) and reset input (R) are 0. The output is 0 if the set input is 0 and the
reset input is 1.
Truth table:
S R D
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
O is the previous cycle output value.
previous
Set input (S): Boolean
Data input (D): Boolean
Clock input (C): Boolean
Reset input (R): Boolean
Output (O): Boolean
C O
previous
0 0
0 -> 1 0
0 0
0 -> 1 0
0 1
0 -> 1 0
0 0
0 -> 1 0
0 0
0 -> 1 1
0 1
0 -> 1 1
0 1
0 -> 1 0
0 0
0 -> 1 0
SR block:
O
0 (= Previous output value)
0 (= Data input value)
0 (= Previous output value)
1 (= Data input value)
0 (Reset)
0 (Reset)
0 (Reset)
0 (Reset)
1 (= Set value)
0 (= Data input value) for
one execution cycle, then
changes to 1 according to
the set input (S = 1).
1 (= Set value)
1 (= Data input value)
0 (Reset)
0 (Reset)
0 (Reset)
0 (Reset)
Standard function blocks
267