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3.3.2
Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3
Interrupt Control Registers
Name
Interrupt edge select register
Interrupt enable register 1
Interrupt enable register 2
Interrupt request register 1
Interrupt request register 2
Wakeup interrupt request register
Note: * Write is enabled only for writing of 0 to clear a flag.
Interrupt Edge Select Register (IEGR)
Bit
Initial value
Read/Write
IEGR is an 8-bit read/write register, used to designate whether pins IRQ
edge sensing or falling edge sensing.
Bit 7—Reserved Bit: Bit 7 is reserved: it is always read as 0, and should be used cleared to 0.
Bits 6 and 5—Reserved Bits: Bits 6 and 5 are reserved; they are always read as 1, and cannot be
modified.
Edge Select (IEG4): Bit 4 selects the input sensing of pin IRQ
Bit 4—IRQ
4
Bit 4: IEG4
0
1
Abbreviation
IEGR
IENR1
IENR2
IRR1
IRR2
IWPR
7
6
—
—
—
0
1
—
—
—
Description
Falling edge of IRQ
/ADTRG pin input is detected
4
Rising edge of IRQ
/ADTRG pin input is detected
4
R/W
R/W
R/W
R/W
R/W*
R/W*
R/W*
5
4
IEG4
IEG3
1
0
R/W
R/W
Initial Value
H'60
H'00
H'01
H'20
H'03
H'00
3
2
IEG2
IEG1
0
0
R/W
R/W
to IRQ
are set to rising
0
4
/ADTRG.
4
Address
H'FFF2
H'FFF3
H'FFF4
H'FFF6
H'FFF7
H'FFF9
1
0
IEG0
0
0
R/W
(initial value)
61
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