Test Access Port (Tap) Connection; Signals With Odt - Intel BX80613I7980 Datasheet

Table 2-3. Signal Groups (Sheet 2 of 2)
Signal Group
Single ended
Single ended
Reset Signal
Single ended
PWRGOOD Signals
Single ended
Power/Other
Notes:
1. Refer to
2. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.
Table 2-4.

Signals with ODT

• QPI_DRX_DP[19:0], QPI_DRX_DN[19:0], QPI_DTX_DP[19:0], QPI_DTX_DN[19:0], QPI_CLKRX_D[N/P],
QPI_CLKTX_D[N/P]
• DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][7:0], DDR{0/1/2}_PAR_ERR#[0:2], VDDPWRGOOD
• BCLK_ITP_D[N/P]
• PECI
• BPM#[7:0], PREQ#, TRST#, VCCPWRGOOD, VTTPWRGOOD
Note:
1. Unless otherwise specified, signals have ODT in the package with 50  pulldown to V
2. PREQ#, BPM[7:0], TDI, TMS and BCLK_ITP_D[N/P] have ODT in package with 35  pullup to V
3. VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 10 k to 20 k pulldown
to V
SS
4. TRST# has ODT in package with a 1 k to 5 k pullup to V
5. All DDR signals are terminated to VDDQ/2
6. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.
7. While TMS and TDI do not have On-Die Termination, these signals are weakly pulled up using a 1–5 k
resistor to V
8. While TCK does not have On-Die Termination, this signal is weakly pulled down using a 1–5 kresistor to
V .
SS
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
at least eight BCLKs for the processor to recognize the proper signal state. See
Section 2.11
requirements for entering and leaving the low power states.
2.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Two copies of each signal may be
required with each driving a different voltage level.
20
Type
CMOS Output
Analog Input
Reset Input
Asynchronous Input
Power
Asynchronous CMOS Output
Sense Points
Other
Chapter 5 for signal descriptions.
.
TT
for the DC specifications. See
Signals
VTT_VID[4:2]
ISENSE
RESET#
VCCPWRGOOD, VTTPWRGOOD, VDDPWRGOOD
VCC, VTTA, VTTD, VCCPLL, VDDQ
PSI#
VCC_SENSE, VSS_SENSE
SKTOCC#, DBR#
.
TT
Chapter 6 for additional timing
Electrical Specifications
1,2
.
SS
.
TT
Datasheet, Volume 1