Test Access Port (Tap) Connection - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet

Electrical Specifications
Table 2-40. RESET_N and SKTID Timing (Sheet 2 of 2)
Parameter
T11
T12
T13
T14
2.14

Test Access Port (TAP) Connection

The recommended TAP connectivity is detailed in the Intel
Port Design Guide (DPDG).
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Description
RESET_N deasserted delay to SKTID[2]
deasserted (as error in)
SKTID[2] (as error in) asserted pulse width
BOOTMODE[2:0], FLASHROM_CFG[1:0] hold
after RESET_N deasserted
BOOTMODE[2:)], FLASHROM_CFG[1:0] setup to
RESET_N asserted
MIN
3
1
0
®
Itanium
§
MAX UNIT
100 ns
SYSCLK
cycles
us
ns
®
Platform Debug
71