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Table 7-38.Signal Groups
Signal Group
Integrated Graphics
Single Ended
Single Ended
PCI Express* Graphics
Differential
Differential
Single Ended
DMI
Differential
Differential
Intel® FDI
Single Ended
Differential
NOTES:
1.
Refer to
Chapter 6
2.
SA and SB refer to DDR3 Channel A and DDR3 Channel B.
3.
These signals are only applicable for the BGA package
4.
These signals are only applicable for the rPGA988A package.
All Control Sideband Asynchronous signals are required to be asserted/deasserted for
at least eight BCLKs in order for the processor to recognize the proper signal state. See
Section 7.10
7.7
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, Intel recommends the processor be first in the TAP chain, followed by any other
components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of
the appropriate voltage. Two copies of each signal may be required with each driving a
different voltage level.
92
1
(Sheet 3 of 3)
Alpha
Type
Group
(aa)
Analog Input
(ab)
CMOS Output
(ac)
PCI Express Input
(ad)
PCI Express Output
(ae)
Analog Input
(af)
DMI Input
(ag)
DMI Output
(ah)
CMOS Input
(ai)
Analog Output
for signal description details.
for the DC specifications.
Electrical Specifications
Signals
GFX_IMON
GFX_VID[6:0], GFX_VR_EN, GFX_DPRSLPVR
PEG_RX[15:0], PEG_RX#[15:0]
PEG_TX[15:0], PEG_TX#[15:0]
PEG_ICOMP0, PEG_ICOMPI, PEG_RCOMP0,
PEG_RBIAS
DMI_RX[3:0], DMI_RX#[3:0]
DMI_TX[3:0], DMI_TX#[3:0]
FDI_FSYNC[1:0], FDI_LSYNC[1:0], FDI_INT
FDI_TX[7:0], FDI_TX#[7:0]
Datasheet
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