Interrupts; Software Reset - Xilinx CAN FD v2.0 Product Manual

cleared during core operation, Xilinx recommends resetting the core so that operation
starts over.
The Object layer is reset synchronously with respect to the above mentioned two sources
(that is, internal reset assertion and deassertion to Object layer is done synchronous to
AXI4-Lite/APB clock).
The Transfer layer is reset asynchronously with respect to the above mentioned three
sources (that is, internal reset assertion to the Transfer layer is asynchronous whereas reset
deassertion is achieved synchronously with respect to the CAN clock). When the Transfer
layer is reset, the core loses synchronization with the CAN bus and drives the recessive bit
on the TX line.
System (Hard) Reset
The system (hard) reset can be enabled by driving a 0 on the reset input port. All of the
configuration registers are reset to their default values. Read/write transactions cannot be
performed when the reset input is 0. When system reset is applied, the ongoing AXI4-Lite/
APB transaction might terminate abruptly. In general, the system reset pulse should be
greater than at least two CAN clock cycles.
Because the Transfer layer is reset asynchronously, ensure that the reset line is glitch-free.
IMPORTANT:

Software Reset

The software reset can be enabled by writing a 1 to the SRST bit in the SRR register. When
a software reset is asserted, all the configuration registers including the SRST bit in the SRR
register are reset to their default values. Read/write transactions can be performed starting
at the next valid transaction window (which starts after sixteen AXI4-Lite/APB clock cycles
after asserting the software reset).
The contents of the TX block RAM and RX block RAM are not cleared when any reset is
IMPORTANT:
applied.

Interrupts

The core has a single interrupt output to indicate an interrupt. Interrupts are indicated by
asserting the ip2bus_intrevent line (transition of the line from a logic 0 to a logic 1).
Interrupt assertion and deassertion is synchronous to the AXI4-Lite/APB clock.
Events such as errors on the bus line, message transmission and reception, and various
other conditions can generate interrupts. During power on, the interrupt line is driven Low.
CAN FD v2.0
PG223 December 5, 2018 www.xilinx.com
Chapter 3: Designing with the Core
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