Xilinx CAN FD v2.0 Product Manual page 29

Table 2-14: Interrupt Clear Register (Cont'd)
Bits Name
2 CPEE
1 CTXOK
0 CARBLOST
Timestamp Register (Address Offset + 0x0028)
A 16-bit free running counter increments once every sixteen CAN clock cycles. A timestamp
is captured after the SOF bit; that is, when the ID field starts on the CAN bus. It is stamped
in DLC field of the message element when frame is successfully received or transmitted. The
timestamp counter can be reset by software. There is no register bit to indicate counter
rollover.
Table 2-15: Timestamp Register
Bits Name
31:16 TIMESTAMP_CNT[15:0]
15:1 Reserved
0 CTS
Data Phase Baud Rate Prescaler Register (Address Offset + 0x0088)
Table 2-16: Data Phase Baud Rate Prescaler Register
Bits Name Access
31:17 Reserved
16 TDC R/W
15:14 Reserved
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
• 1 = Clears Protocol Exception Event interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
W 0 • 1 = Clears Transmission Successful interrupt status bit.
• 1 = Clears Arbitration Lost interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
Access Default
Value
Timestamp Counter Value.
This Status field gives running value of the timestamp counter.
R 0
This field is cleared when a 0 is written to the CEN bit in the
SRR.
– 0 Reserved
Clear Timestamp Counter.
Internal free running counter is cleared to 0 when CTS = 1.
W 0
This bit only needs to be written once with a 1 to clear the
counter.
The bit always reads as 0.
Default
Value
– 0 Reserved
Transmitter Delay Compensation (TDC) Enable
• 1 = Enables TDC function as specified in the CAN FD standard.
0
• 0 = TDC is disabled.
This bit can be written only when CEN bit in SRR is 0.
– 0 Reserved
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Chapter 2: Product Specification
Description
Description
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