Xilinx CAN FD v2.0 Product Manual page 26

Table 2-13: Interrupt Enable Register (Cont'd)
Bits Name
ERXBOFLW/
16
ERXFWMFLL_1
ERXRBF/
15
ERXFOFLW_1
14 ETXCRS
13 ETXRRS
12 ERXFWMFLL
11 EWKUP
10 ESLP
9 EBSOFF
8 EERROR
7 Reserved
6 ERFXOFLW
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
RX Buffer Overflow interrupt Enable (Mailbox mode).
• 1 = Enables interrupt generation if RXBOFLW bit in the ISR is set.
• 0 = Disables interrupt generation if RXBOFLW bit in the ISR is set.
R/W 0
RX FIFO-1 Watermark Full Interrupt Enable (Sequential/FIFO Mode).
• 1 = Enables interrupt generation if RXFWMFLL_1 bit in the ISR is set.
• 0 = Disables interrupt generation if RXFWMFLL_1 bit in the ISR is
set.
RX Buffer Bull Interrupt Enable (Mailbox mode).
• 1 = Enables interrupt generation if RXRBF bit in the ISR is set.
• 0 = Disables interrupt generation if RXRBF bit in the ISR is set.
R/W 0
RX FIFO-1 Overflow Interrupt Enable (Sequential/FIFO Mode).
• 1 = Enables interrupt generation if RFXOFLW_1 bit in the ISR is set.
• 0 = Disables interrupt generation if RFXOFLW_1 bit in the ISR is set.
TX Cancellation Request Served Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if TXCRS bit in the ISR is set.
• 0 = Disables interrupt generation if TXCRS bit in the ISR is set.
TX Buffer Ready Request Served Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if TXRRS bit in the ISR is set.
• 0 = Disables interrupt generation if TXRRS bit in the ISR is set.
RX FIFO-0 Watermark Full Interrupt Enable (Sequential/FIFO Mode).
R/W 0 • 1 = Enables interrupt generation if RXFWMFLL bit in the ISR is set.
• 0 = Disables interrupt generation if RXFWMFLL bit in the ISR is set.
Wake-Up Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if WKUP bit in the ISR is set.
• 0 = Disables interrupt generation if WKUP bit in the ISR is set.
Sleep Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if SLP bit in the ISR is set.
• 0 = Disables interrupt generation if SLP bit in the ISR is set.
Bus-Off Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if BSOFF bit in the ISR is set.
• 0 = Disables interrupt generation if BSOFF bit in the ISR is set.
Error Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if ERROR bit in the ISR is set.
• 0 = Disables interrupt generation if ERROR bit in the ISR is set.
– 0 Reserved
RX FIFO-0 Overflow Interrupt Enable (Sequential/FIFO Mode).
R/W 0 • 1 = Enables interrupt generation if RFXOFLW bit in the ISR is set.
• 0 = Disables interrupt generation if RFXOFLW bit in the ISR is set.
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Chapter 2: Product Specification
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