Xilinx CAN FD v2.0 Product Manual page 64

X-Ref Target - Figure 3-1
Core Operating Modes
PEE
BSFR
Table 3-1: CAN FD Core Operating Mode Transitions
SRR
Register MSR Register Bits
System
Bits
(Hard)
Reset
SRST
(SW CEN LBACK SLEEP SNOOP Config
Reset)
0
X X
(reset)
1
1 X
(reset)
CAN FD v2.0
PG223 December 5, 2018
System (Hard) or Soft Reset or CEN = 0
Normal
Sleep
After reset when CEN = 1, core exits Configuration mode after detecting 11
consecutive recessive bits on the CAN bus.
Figure 3-1: Core Operating Modes
Config
X X X 1
X X X 1
www.xilinx.com
Chapter 3: Designing with the Core
Snoop
Config
Lback
SR (Status) Register Bits
BSFR_ PEE_
LBACK SLEEP NORMAL SNOOP
Config
0 0 0 0
0 0 0 0
PEE
X14812-081518
Operation Mode
Core is under
0 0
reset
Core is under
0 0
reset
Send Feedback
64