Xilinx CAN FD v2.0 Product Manual page 28

Table 2-14: Interrupt Clear Register (Cont'd)
Bits Name
CRXRBF/
15
CRXFWMFLL_1
14 CTXCRS
13 CTXRRS
12 CRXFWMFLL
11 CWKUP
10 CSLP
9 CBSOFF
8 CERROR
7 Reserved
6 CRFXOFLW
5 ETSCNT_OFLW
4 CRXOK
3 CBSFRD
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
• 1 = Clears RX Buffer Bull Interrupt status bit (Mailbox mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
W 0
• 1 = Clears RX FIFO-1 Overflow interrupt status bit (Sequential/
FIFO Mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears TX Cancellation Request Served Interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears TX Buffer Ready Request Served Interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears RX FIFO-0 Watermark Full interrupt status bit
(Sequential/FIFO Mode).
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Wake-Up interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Sleep interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Bus-Off interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Error interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
– 0 Reserved.
• 1 = Clears RX FIFO-0 Overflow interrupt status bit (Sequential/
FIFO Mode).
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Timestamp Counter Overflow Interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads always 0.
• 1 = Clears New Message Received interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Bus-Off Recovery Done interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
www.xilinx.com
Chapter 2: Product Specification
Description
Send Feedback
28