Chapter 1: Overview - Xilinx CAN FD v2.0 Product Manual

Overview
This product guide describes features of the CAN FD core and the functionality of the
various registers in the design. In addition, the core interface and its customization options
are defined in this document. Information on the CAN or CAN FD protocol is outside the
scope of this document, and knowledge of the relevant CAN and CAN FD specifications is
assumed. Figure 1-1
the interface connectivity.
X-Ref Target - Figure 1-1
Host
Control
Figure 1-1: CAN FD Core Layered Architecture and Connectivity
The core requires an external PHY to be connected to communicate on the CAN bus.
Note:
CAN FD v2.0
PG223 December 5, 2018
illustrates the high-level architecture of the CAN FD core and provides
CAN FD Core
Object Layer/LLC
TBMM
TX Block
RAM
AXI4-Lite
Register Module
I/F
RBMM
RX Block
RAM
AXI Clock Domain
www.xilinx.com
Transfer Layer/MAC
CDC
CAN FD Protocol Engine
Sync
CAN Clock Domain
Chapter 1
TX
PHY
RX
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