Xilinx CAN FD v2.0 Product Manual page 24

Table 2-12: Interrupt Status Register (Cont'd)
Access Default
Bits Name
13 TXRRS
12 RXFWMFLL
11 WKUP
10 SLP
9 BSOFF
8 ERROR
7 Reserved
6 RXFOFLW
5 TSCNT_OFLW
4 RXOK(1)
CAN FD v2.0
PG223 December 5, 2018
Value
TX Buffer Ready Request Served Interrupt.
R 0 • 1 = Indicates that a Buffer Ready request was cleared.
This bit can be cleared by writing to the respective bit in the ICR.
RX FIFO-0 Watermark Full Interrupt (Sequential/FIFO Mode).
• 1 = Indicates that RX FIFO-0 is full based on watermark
programming.
R 0
The interrupt continues to assert as long as the RX FIFO-0 Fill Level is
above RX FIFO-0 Full watermark.
This bit can be cleared by writing to the respective bit in the ICR.
Wake-Up Interrupt
• 1 = Indicates that the core entered Normal mode from Sleep mode.
R 0
This bit can be cleared by writing to the respective bit in the ICR. This
bit is also cleared when a 0 is written to the CEN bit in the SRR.
Sleep Interrupt.
• 1 = Indicates that the CAN core entered Sleep mode.
R 0
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
Bus-Off Interrupt.
• 1 = Indicates that the CAN core entered the Bus-Off state.
R 0
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
Error Interrupt.
• 1 = Indicates that an error occurred during message transmission or
reception.
R 0
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
– 0 Reserved.
RX FIFO-0 Overflow Interrupt (Sequential/FIFO Mode).
• 1 = Indicates that a message has been lost. This condition occurs
when a new message with ID matching to RX FIFO-0 is received and
R 0
the RX FIFO-0 is full.
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
Timestamp Counter Overflow Interrupt.
• 1 = Indicates that Timestamp counter rolled over (from 0xffff to 0x0).
R 0
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
New Message Received Interrupt
• 1 = Indicates that a message was received successfully and stored
into the RX FIFO-0 or RX FIFO-1 or RX Mailbox buffer.
R 0
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
www.xilinx.com
Chapter 2: Product Specification
Description
Send Feedback
24