Xilinx CAN FD v2.0 Product Manual page 15

Table 2-4: CAN FD Core Register Space (Cont'd)
Start
Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0x00F8
RSVD
0x00FC
RSVD
Notes:
1. These fields are only available when the IP is configured in FIFO (Sequential) Mode and RX FIFO-1 is enabled.
Software Reset Register (Address Offset + 0x0000)
Writing to the Software Reset register (SRR) places the core in Configuration mode. In
Configuration mode, the core drives recessive on the bus line and does not transmit or
receive messages. During power-up, the CEN and SRST bits are 0 and the CONFIG bit in the
Status register (SR) is 1. The Transfer Layer Configuration registers can be changed only
when the CEN bit in the SRR is 0. Mode Select register bits (except SLEEP and SBR) can be
changed only when the CEN bit is 0. If the CEN bit is changed during core operation, Xilinx
recommends resetting the core so that operation starts over.
Table 2-5: Software Reset Register
Bits Name
31:2 Reserved
1 CEN
0 SRST
Mode Select Register (Address Offset + 0x0004)
Writing to the Mode Select register (MSR) enables the core to enter Snoop, Sleep,
Loopback, or Normal modes. In Normal mode, the core participates in normal bus
communication. If the SLEEP bit is set to 1, the core enters Sleep mode. If the LBACK bit is
set to 1, the core enters Loopback mode. If the SNOOP mode is set to 1, the core enters
Snoop mode and does not participate in bus communication but only receives messages.
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
– 0 Reserved.
CAN Enable.
This is the Enable bit for the core.
• 1 = The core is in Loopback, Sleep, Snoop, or Normal mode,
R/W 0
depending on the LBACK, SLEEP, and SNOOP bits in the MSR.
• 0 = The core is in Configuration mode.
If the CEN bit is cleared during core operation, Xilinx recommends
Note:
resetting the core so that operation starts over.
Reset.
This is the software reset bit for the core.
• 1 = Core is reset.
WO 0
If a 1 is written to this bit, all core configuration registers
(including the SRR) are reset. Reads to this bit always return 0.
After performing a soft or hard reset, wait for 16 AXI4-Lite/APB
Note:
clock cycles before initiating next AXI4-Lite/APB transaction.
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Chapter 2: Product Specification
8 7 6 5 4 3 2
Description
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Name
1 0 (Reset
Value)
Reserved
Reserved
15