Xilinx CAN FD v2.0 Product Manual page 11

Table 2-2: CAN FD Address Space Division
Start Address End Address
0x0000
0x0100
0x2000
Table 2-3: CAN FD Core Register Address Map
Start
Name
Address
0x0000 SRR
0x0004 MSR
0x0008 BRPR
0x000C BTR
0x0010 ECR
0x0014 ESR
0x0018 SR
0x001C ISR
0x0020 IER
0x0024 ICR
0x0028 TSR
0x002C-
Reserved
0x0084
0x0088 DP_BRPR
0x008C DP_BTR
0x0090 TRR
0x0094 IETRS
CAN FD v2.0
PG223 December 5, 2018
Section
0x00FF Core Registers Space
0x1FFF TX Message Space
0x7FFF RX Message Space
Access
Read, Write Software Reset Register
Read, Write Mode Select Register
Arbitration Phase Baud Rate Prescaler
Read, Write
Register
Read, Write Arbitration Phase Bit Register
Read Error Counter Register
Read, Write
Error Status Register
1 to clear
Read Status Register
Read Interrupt Status Register
Read, Write Interrupt Enable Register
Write Interrupt Clear Register
Read, Write Timestamp Register
Reserved space. Write has no effect. Read
–
always returns 0.
Read, Write Data Phase Baud Rate Prescaler Register
Read, Write Data Phase Bit Timing Register
Read, Write TX Buffer Ready Request Register
Interrupt Enable TX Buffer Ready Request
Read, Write
Served/Cleared Register
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Chapter 2: Product Specification
Notes
This space is implemented with flip-flops. See
Table 2-3 and Table 2-4.
This space is implemented with TX block RAM
and provides storage for a maximum 32 TX
buffers. For RX Sequential buffer mode (FIFO
mode), it also
provides storage for 32 ID Filter-Mask pairs. See
Table 2-30.
This space is implemented with RX block RAM.
For RX Sequential buffer mode (FIFO mode), it
provides storage for two 64-deep message RX
FIFO's. See Table 2-37 and
It provides storage for 32 deep TX Event FIFO.
See Table 2-34.
For RX Mailbox buffer mode, it provides storage
for maximum 48 RX Buffers and respective ID
Masks. See Table 2-44.
Description
Send Feedback
Table 2-38.
Notes
Registers present in
both RX Mailbox
and RX Sequential/
FIFO buffer modes.
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