Xilinx CAN FD v2.0 Product Manual page 72

3. If the TXB_i buffer has a pending transmission request but no pending cancellation
request, Transmit Cancellation can be requested as follows:
a. Enable interrupt generation if/as required.
b. Set the required CR bit/bits of the TCR register. The Host can request the cancellation
of many buffers in one write to the TCR register.
c. Wait for interrupt or poll the TCR register to check the cancellation status.
4. The CAN FD clears the bit in the TCR register when the respective buffer transmit
cancellation request is completed.
5. The CAN FD also clears the corresponding bit in the TRR register when cancellation is
performed.
TC – Core Actions
1. The CAN FD performs the cancellation of a buffer immediately, except in the following
conditions:
a. When the buffer is locked by the Transfer Layer for transmission on the CAN bus. In
this case, cancellation is performed at the end of transmission irrespective of
whether the transmission succeeds or fails (arbitration loss or error).
b. When the core is performing a scheduling round to find out the next buffer for
transmission. In this case, cancellation is performed after the scheduling round is
over.
2. The CAN FD clears respective bits in the TCR and TRR registers when cancellation is
done.
3. If enabled through IETCS and IER, the TXRCS bit is set in the ISR register (when the core
clears the bit in the TCR register) and interrupt is generated.
Reception (Sequential Buffer/FIFO Mode)
Whenever a new message (that passes the required filtering) is stored into RX FIFOs, the
core updates the respective Fill Level field of the FSR register and sets the RXOK bit in the
ISR register.
RX – Host Actions
1. As per requirement, program the RX FIFO Watermark register to set Full Watermarks and
RXFP field (RX FIFO Watermark Register can be set/changed only when CEN = 0).
2. If required, enable RXOK and RX Overflow interrupt generation.
3. New message availability can be found by polling FSR register or by Watermark Full
interrupts indication.
4. Read a new message (from RX FIFO-0 or RX FIFO-1) starting from its respective Read
Index location (given in FSR register field).
CAN FD v2.0
PG223 December 5, 2018 www.xilinx.com
Chapter 3: Designing with the Core
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