Xilinx CAN FD v2.0 Product Manual page 12

Table 2-3: CAN FD Core Register Address Map (Cont'd)
Start
Name
Address
0x0098 TCR
0x009C IETCS
0x00A0 TxE_FSR
0x00A4 TxE_WMR
0x00A8-
Reserved
0x00AC
0x00B0 RCS0
0x00B4 RCS1
0x00B8 RCS2
0x00BC Reserved
0x00C0 IERBF0
0x00C4 IEBRF1
0x00C8-
Reserved
0x00DC
0x00E0 AFR
0x00E4 Reserved
0x00E8 FSR
0x00EC WMR
0x00F0-
Reserved
0x00FF
Core Register Descriptions
Table 2-4 shows the CAN FD core register space. The thick ruling represents the RX Mailbox
specific register bits and the gray represents the RX FIFO specific register bits. Register bits
that are used in both RX Mailbox and RX FIFO mode and differ in description are shown with
a / separator.
Table 2-4: CAN FD Core Register Space
Start
Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0x0000 RSVD
0x0004
RSVD
CAN FD v2.0
PG223 December 5, 2018
Access
Read, Write TX Buffer Cancel Request Register
Interrupt Enable TX Buffer Cancellation
Read, Write
Request Served/Cleared Register
Read, Write TX Event FIFO Status Register.
Read, Write TX Event FIFO Watermark Register.
Reserved space. Write has no effect. Read
–
always returns 0.
Read, Write RX Buffer Control Status Register 0
Read, Write
See RX Buffer Control Status Register 0
Read, Write
Reserved space. Write has no effect. Read
–
always returns 0.
Read, Write Interrupt Enable RX Buffer Full Register 0
Read, Write Interrupt Enable RX Buffer Full Register 1
Reserved space. Write has no effect. Read
–
always returns 0.
Read, Write Acceptance Filter (Control) Register
Reserved space. Write has no effect. Read
–
always returns 0.
Read, Write RX FIFO Status Register
Read, Write RX FIFO Watermark Register
Reserved space. Write has no effect. Read
–
always returns 0.
RSVD
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Chapter 2: Product Specification
Description
8 7 6 5
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Notes
Registers present in
both RX Mailbox
and RX Sequential/
FIFO buffer modes.
Registers present
only in RX Mailbox
buffer mode.
Otherwise reserved.
Registers present
only in RX
Sequential/FIFO
buffer mode
otherwise reserved.
Name
4 3 2 1 0 (Reset
Value)
SRR (0x0)
MSR (0x0)
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