Xilinx CAN FD v2.0 Product Manual page 95

Output s_axi_arready asserts when the read address is valid, and output
s_axi_rvalid asserts when the read data/response is valid. If the interface is
unresponsive, ensure that the following conditions are met:
• The s_axi_aclk and can_clk inputs are connected and toggling.
• The interface is not being held in reset, and s_axi_areset is an active-Low reset.
• The interface is enabled, and s_axi_aclken is active-High (if used).
• The main core clocks are toggling and that the enables are also asserted.
• If the simulation has been run, verify in simulation and/or in the Vivado Design Suite
debug feature capture that the waveform is correct for accessing the AXI4-Lite
interface.
CAN FD v2.0
PG223 December 5, 2018 www.xilinx.com
Appendix C: Debugging
95
Send Feedback